NBSG16M: Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer

内容: The NBSG16M is a differential current mode logic (...
  • The NBSG16M is a differential current mode logic (CML) receiver/driver. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.
    Inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 Ω source termination resistor to VCC. The device generates 400 mV output amplitude with 50 Ω receiver resistor to VCC.
    The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.
  • 特長
  • Maximum Input Clock Frequency > 10 GHz Typical
  • Maximum Input Data Rate > 10 Gb/s Typical
  • 120 ps Typical Propagation Delay
  • 35 ps Typical Rise and Fall Times
  • Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • CML Output Level; 400 mV Peak-to-Peak Output with 50 _ Receiver Resistor to VCC
  • 50 Ω Internal Input and Output Termination Resistors
  • Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices
  • VBB Reference Voltage Output
  • Pb-Free Packages are Available
  • アプリケーション
  • Backplane buffering
  • OC-3 through OC-192 clock or data distribution/driver
  • Gigabit Ethernet clock or data driver
  • Fibre Channel distribution/driver
  • 技術資料 & デザイン・リソース
    評価/開発ツール情報
    製品変更通知
    供給状況 & サンプル
    NBSG16MMNG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer
  • 外形 タイプ: QFN-16
  • 外形 Case Outline: 485G-01
  • MSL: 1
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 123
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Avnet:<100
  • Digikey:<1K
  • ON Semiconductor:4,182
  • パッケージ
    Specifications
  • Type: Signal Driver 
  • Channels:
  • Input / Output Ratio: 1:1 
  • Input Level: LVDS  CMOS  CML  ECL  TTL 
  • Output Level: CML 
  • VCC Typ (V): 2.5  3.3 
  • tJitterRMS Typ (ps): 0.2 
  • tskew(o-o) Max (ps):  
  • tpd Typ (ns): 0.12 
  • tR & tF Max (ps): 53 
  • fmaxClock Typ (MHz): 10000 
  • fmaxData Typ (Mbps): 10000 
  • Package Type: QFN-16 
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