MC10EP451: 3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset
内容: The MC10/100EP451 is a 6-bit fully differential re...
The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.
The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.
The 100 Series contains temperature compensation.
450 ps Typical Propagation Delay
Maximum Frequency > 3.0 GHz Typical
Asynchronous Master Reset
20 ps Skew Within Device, 35 ps Skew Device-To-Device
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available
High Performance Logic for test systems
供給状況 & サンプル
Compliance: Pb-free Halide free
内容: 3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset
外形 タイプ: LQFP-32
外形 Case Outline:
梱包形態 タイプ: JTRAY
梱包形態 数量: 250
Market Leadtime (weeks):2 to 4
VCC Typ (V):
tJitter Typ (ps):
tpd Typ (ns):
tsu Min (ns):
th Min (ns):
trec Typ (ns):
tR & tF Max (ps):
fToggle Typ (MHz):