MC10EP29: 3.3 V / 5.0 V ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

内容: The MC10/100EP29 is a dual master-slave flip flop....
  • The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.

    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.

    Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.

    The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

    The 100 Series Contains Temperature Compensation
  • 特長
  • Maximum Frequency > 3 GHz Typical
  • 500 ps Typical Propagation Delays
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • These are Pb−Free Devices
  • アプリケーション
  • Functionally equivalent to the MC10/100EL29
  • 技術資料 & デザイン・リソース
    供給状況 & サンプル
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 3.3 V / 5.0 V ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset
  • 外形 タイプ: TSSOP-20
  • 外形 Case Outline: 9.48
  • MSL: 1
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 75
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Digikey:<100
  • ON Semiconductor:4,425
  • パッケージ
  • Type: D-Type 
  • Bits:
  • Input Level: ECL  CML 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • tJitter Typ (ps): 0.2 
  • tpd Typ (ns): 0.42 
  • tsu Min (ns): 0.1 
  • th Min (ns): 0.1 
  • trec Typ (ns): 0.08 
  • tR & tF Max (ps): 250 
  • fToggle Typ (MHz): 3000 
  • Package Type: TSSOP-20 
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