MC10EP131: 3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
内容: The MC10EP131 is a Quad Master-slaved D flip-flop ...
The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.
Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and (CCbar) HIGH, then using the Clock Enable inputs for clocking (C0-3 and C0-3bar).
Common clocking is achieved by holding the C0-3 inputs LOW and C0-3bar inputs HIGH while using the differential common clock CC to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.
Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided.
Data enters the master when both CC and C0-3 are LOW, and transfers to the slave when either CC or C0-3 (or both) go HIGH.
The 100 Series contains temperature compensation.
460ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available
High Performance Logic for test systems
供給状況 & サンプル
Compliance: Pb-free Halide free
内容: 3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
外形 タイプ: LQFP-32
外形 Case Outline:
梱包形態 タイプ: JTRAY
梱包形態 数量: 250
Market Leadtime (weeks):2 to 4
VCC Typ (V):
tJitter Typ (ps):
tpd Typ (ns):
tsu Min (ns):
th Min (ns):
trec Typ (ns):
tR & tF Max (ps):
fToggle Typ (MHz):