MC10E111: 5.0 V ECL 1:9 Differential Clock Driver

内容: The MC10E/100E111 is a low skew 1-to-9 differentia...
  • The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Qbar outputs HIGH.

    The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

    To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 , even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO ) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.

    The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

    The 100 Series contains temperature
  • 特長
  • Guaranteed Skew Spec
  • Differential Design
  • VBB Output
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
    with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V
    with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 3 KV HBM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1 (For Additional Information, see Application Note AND8003/D)
  • Flammability Rating: UL-94 code V-0 @ 1/8 inch, Oxygen Index 28 to 34
  • Transistor Count = 178 devices
  • Pb-Free Packages are Available
  • 技術資料 & デザイン・リソース
    供給状況 & サンプル
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 5.0 V ECL 1:9 Differential Clock Driver
  • 外形 タイプ: PLCC-28
  • 外形 Case Outline: 776-02
  • MSL: 3
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 37
  • 在庫

  • Market Leadtime (weeks):2 to 4
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  • Digikey:<100
  • ON Semiconductor:2,035
  • MC10E111FNR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 5.0 V ECL 1:9 Differential Clock Driver
  • 外形 タイプ: PLCC-28
  • 外形 Case Outline: 776-02
  • MSL: 3
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 500
  • 在庫

  • Market Leadtime (weeks):13 to 16
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  • ON Semiconductor:2,000
  • PandS:<1K
  • パッケージ
  • Type: Buffer 
  • Channels:
  • Input / Output Ratio: 1:9 
  • Input Level: ECL 
  • Output Level: ECL 
  • VCC Typ (V):
  • tJitterRMS Typ (ps): <1 
  • tskew(o-o) Max (ps): 75 
  • tpd Typ (ns): 0.53 
  • tR & tF Max (ps): 650 
  • fmaxClock Typ (MHz): 800 
  • fmaxData Typ (Mbps):  
  • Package Type: PLCC-28 
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