MC100LVEP14: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

内容: The MC100LVEP14 is a low skew 1 to 5 differential ...
  • The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
  • 特長
  • 100 ps Device-to-Device Skew
  • 25 ps Within Device Skew
  • 400 ps Typical Propagation Delay
  • Maximum Frequency > 2 GHz Typical
  • PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • LVDS Input Compatible
  • Open Input Default State
  • 技術資料 & デザイン・リソース
    製品変更通知
    供給状況 & サンプル
    MC100LVEP14DTG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
  • 外形 タイプ: TSSOP-20
  • 外形 Case Outline: 9.48
  • MSL: 1
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 75
  • 在庫

  • Market Leadtime (weeks):2 to 4
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  • Digikey:<100
  • FutureElectronics:<100
  • MC100LVEP14DTR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
  • 外形 タイプ: TSSOP-20
  • 外形 Case Outline: 9.48
  • MSL: 1
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 2500
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • ON Semiconductor:102,059
  • パッケージ
    Specifications
  • Type: Buffer 
  • Channels:
  • Input / Output Ratio: 2:1:5 
  • Input Level: HSTL  CML  ECL  LVDS 
  • Output Level: ECL 
  • VCC Typ (V): 2.5  3.3 
  • tJitterRMS Typ (ps): 0.181 
  • tskew(o-o) Max (ps): 25 
  • tpd Typ (ns): 0.4 
  • tR & tF Max (ps): 225 
  • fmaxClock Typ (MHz): 2000 
  • fmaxData Typ (Mbps):  
  • Package Type: TSSOP-20 
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