MC100LVEL14: 3.3 V ECL 1:5 Clock Distribution Chip

内容: The MC100LVEL14 is a low skew 1:5 clock distributi...
  • The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0 V to -3.8 V ( or 3.0 V to 3.8 V).

    The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.

    The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

    The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
  • 特長
  • 50 ps Output-to-Output Skew
  • Synchronous Enable/Disable
  • Multiplexed Clock Input
  • ESD Protection: >2 KV HBM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
    with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V
    with VEE = -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors on CLK
  • Q Output will Default LOW with Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8",
    Oxygen Index 28 to 34
  • Transistor Count = 303 devices
  • 技術資料 & デザイン・リソース
    製品変更通知
    供給状況 & サンプル
    MC100LVEL14DWG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 3.3 V ECL 1:5 Clock Distribution Chip
  • 外形 タイプ: SOIC-20W
  • 外形 Case Outline: 751D-05
  • MSL: 3
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 38
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Avnet:<100
  • Digikey:<1K
  • Newark:<100
  • ON Semiconductor:2,356
  • MC100LVEL14DWR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 3.3 V ECL 1:5 Clock Distribution Chip
  • 外形 タイプ: SOIC-20W
  • 外形 Case Outline: 751D-05
  • MSL: 3
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 1000
  • 在庫

  • Market Leadtime (weeks):4 to 8
  • Arrow:0
  • Digikey:>1K
  • パッケージ
    Specifications
  • Type: Buffer 
  • Channels:
  • Input / Output Ratio: 2:1:5 
  • Input Level: ECL  LVDS 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • tJitterRMS Typ (ps): 0.2 
  • tskew(o-o) Max (ps): 50 
  • tpd Typ (ns): 0.68 
  • tR & tF Max (ps): 500 
  • fmaxClock Typ (MHz): 1000 
  • fmaxData Typ (Mbps):  
  • Package Type: SOIC-20W 
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