MC100EP51: ECL D Flip-Flop with Reset and Differential Clock

内容: The MC10/100EP51 is a differential clock D flip-fl...
  • The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.

    The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.

    The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.
  • 特長
  • 350ps Typical Propagation Delay
  • Maximum Frequency > 3 Ghz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Pb-Free Packages are Available
  • アプリケーション
  • ATE
  • 技術資料 & デザイン・リソース
    製品変更通知
    供給状況 & サンプル
    MC100EP51DG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL D Flip-Flop with Reset and Differential Clock
  • 外形 タイプ: SOIC-8
  • 外形 Case Outline: 751-07
  • MSL: 1
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 98
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  • Digikey:<1K
  • FutureElectronics:<1K
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  • MC100EP51DR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL D Flip-Flop with Reset and Differential Clock
  • 外形 タイプ: SOIC-8
  • 外形 Case Outline: 751-07
  • MSL: 1
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 2500
  • 在庫

  • Market Leadtime (weeks):4 to 8
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  • MC100EP51DTG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL D Flip-Flop with Reset and Differential Clock
  • 外形 タイプ: TSSOP-8
  • 外形 Case Outline: 948R-02
  • MSL: 3
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 100
  • 在庫

  • Market Leadtime (weeks):2 to 4
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  • MC100EP51DTR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL D Flip-Flop with Reset and Differential Clock
  • 外形 タイプ: TSSOP-8
  • 外形 Case Outline: 948R-02
  • MSL: 3
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 2500
  • MC100EP51MNR4G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL D Flip-Flop with Reset and Differential Clock
  • 外形 タイプ: DFN-8
  • 外形 Case Outline: 506AA
  • MSL: 1
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 1000
  • 在庫

  • Market Leadtime (weeks):4 to 8
  • Arrow:0
  • Avnet:>1K
  • PandS:<1K
  • パッケージ
    Specifications
  • Type: D-Type 
  • Bits:
  • Input Level: CML  ECL 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • tJitter Typ (ps): 0.2 
  • tpd Typ (ns): 0.32 
  • tsu Min (ns): 0.1 
  • th Min (ns): 0.1 
  • trec Typ (ns): 0.15 
  • tR & tF Max (ps): 170 
  • fToggle Typ (MHz): 3000 
  • Package Type: SOIC-8  TSSOP-8  DFN-8 
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