MC100EP35: ECL JK Flip-Flop

内容: The MC10EP35 is a higher speed/low voltage version...
  • The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

    The 100 Series contains temperature compensation.
  • 特長
  • 410 ps Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
  • アプリケーション
  • Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.
  • 技術資料 & デザイン・リソース
    製品変更通知
    供給状況 & サンプル
    MC100EP35DG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL JK Flip-Flop
  • 外形 タイプ: SOIC-8
  • 外形 Case Outline: 751-07
  • MSL: 1
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 98
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Digikey:<100
  • ON Semiconductor:15,288
  • PandS:<100
  • MC100EP35DTG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL JK Flip-Flop
  • 外形 タイプ: TSSOP-8
  • 外形 Case Outline: 948R-02
  • MSL: 3
  • 梱包形態 タイプ: TUBE
  • 梱包形態 数量: 100
  • MC100EP35DTR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: ECL JK Flip-Flop
  • 外形 タイプ: TSSOP-8
  • 外形 Case Outline: 948R-02
  • MSL: 3
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 2500
  • パッケージ
    Specifications
  • Type: JK-Type 
  • Bits:
  • Input Level: ECL  CML 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • tJitter Typ (ps): 0.2 
  • tpd Typ (ns): 0.41 
  • tsu Min (ns): 0.15 
  • th Min (ns): 0.15 
  • trec Typ (ns): 0.15 
  • tR & tF Max (ps): 170 
  • fToggle Typ (MHz): 3000 
  • Package Type: SOIC-8  TSSOP-8 
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