MC100EP196: 3.3 V ECL Programmable Delay Chip

内容: The MC100EP196 is a programmable delay chip (PDC) ...
  • The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
  • 特長
  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available
  • 技術資料 & デザイン・リソース
    製品変更通知
    供給状況 & サンプル
    MC100EP196FAG
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 3.3 V ECL Programmable Delay Chip
  • 外形 タイプ: LQFP-32
  • 外形 Case Outline: 
  • MSL: 2
  • 梱包形態 タイプ: JTRAY
  • 梱包形態 数量: 250
  • 在庫

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Digikey:<1K
  • PandS:<100
  • MC100EP196FAR2G
  • 状態: Active
  • Compliance: Pb-free Halide free 
  • 内容: 3.3 V ECL Programmable Delay Chip
  • 外形 タイプ: LQFP-32
  • 外形 Case Outline: 
  • MSL: 2
  • 梱包形態 タイプ: REEL
  • 梱包形態 数量: 2000
  • 在庫

  • Market Leadtime (weeks):4 to 8
  • Arrow:0
  • ON Semiconductor:6,000
  • パッケージ
    Specifications
  • Input Level: CML  ECL 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • fMax Typ (MHz): 1200 
  • td(prog) Min (ns): 8.6 
  • td(prog) Max (ns): 12 
  • td(step) Typ (ps): 11 
  • tJitter Typ (ps):
  • tR & tF Max (ps): 200 
  • Package Type: LQFP-32 
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