MC100EP116: Differential Line Receiver / Driver
内容: The MC10EP116/100EP116 is a 6-bit differential lin...
The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC.
The 100 Series contains temperature compensation.
260 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE =-3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
General Purpose Logic
供給状況 & サンプル
Compliance: Pb-free Halide free
内容: Differential Line Receiver / Driver
外形 タイプ: LQFP-32
外形 Case Outline:
梱包形態 タイプ: JTRAY
梱包形態 数量: 250
Market Leadtime (weeks):13 to 16
Input / Output Ratio:
VCC Typ (V):
tJitterRMS Typ (ps):
tskew(o-o) Max (ps):
tpd Typ (ns):
tR & tF Max (ps):
fmaxClock Typ (MHz):
fmaxData Typ (Mbps):