Overview
SYSCLK can be generated from one of five different sources for maximum flexibility. Available sources for SYSCLK include:
- The internal startup system RC clock (discussed in RC Oscillator)
- The RF clock provided by the system crystal clock (discussed in 48 MHz Crystal Oscillator)
- STANDBYCLK
- The SWCLK pad from the SWJ-DP (discussed in Debug Port Clock)
- EXTCLK, provided at a selected GPIO
For more information about configuring SYSCLK, see System Clock (SYSCLK).
Similarly, the STANDBYCLK can be generated from two different sources, including:
- The internal standby RC oscillator (discussed in Standby RC Oscillator)
- The 32 kHz crystal oscillator (discussed in Section 32 kHz Crystal Oscillator)
For more information about configuring STANDBYCLK, see Standby Clock (STANDBYCLK)).
A top-level clock diagram showing the clock generation and distribution of clocks within the RSL15 system is provided in the "Overview" figure.