RF_FRONTEND
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
25:16 |
RW |
RX_IF_DIG_IF_DIG |
IF frequency (banked) |
14:11 |
RW |
FRONTEND_RESAMPLE_PH_GAIN |
Gain of the phase resampling block (banked) |
10:8 |
RW |
FRONTEND_RESAMPLE_RSSI_G2 |
Gain of the decimator in the RSSI resampling block (banked) |
7:6 |
RW |
FRONTEND_RESAMPLE_RSSI_G1 |
Gain of the interpolator in the RSSI resampling block (banked) |
5 |
RW |
FRONTEND_EN_RESAMPLE_RSSI |
RSSI resampling (banked) |
4 |
RW |
FRONTEND_EN_RESAMPLE_PHADC |
Phase resampling (banked) |
3:0 |
RW |
FRONTEND_DIV_PHADC |
Unsigned value that specifies the divider to obtain the phase ADC clock and RSSI (banked) |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
25:16 |
RX_IF_DIG_IF_DIG |
RX_IF_DIG_IF_DIG_DEFAULT |
Signed value equal to f_IF/f_phADC*1024 |
0x40* |
14:11 |
FRONTEND_RESAMPLE_PH_GAIN |
FRONTEND_RESAMPLE_PH_GAIN_DEFAULT |
|
0x6* |
10:8 |
FRONTEND_RESAMPLE_RSSI_G2 |
FRONTEND_RESAMPLE_RSSI_G2_DEFAULT |
|
0x0* |
7:6 |
FRONTEND_RESAMPLE_RSSI_G1 |
FRONTEND_RESAMPLE_RSSI_G1_DEFAULT |
|
0x0* |
5 |
FRONTEND_EN_RESAMPLE_RSSI |
FRONTEND_EN_RESAMPLE_RSSI_DISABLE |
Disable the RSSI resampling |
0x0* |
|
|
FRONTEND_EN_RESAMPLE_RSSI_ENABLE |
Enable the RSSI resampling |
0x1 |
4 |
FRONTEND_EN_RESAMPLE_PHADC |
FRONTEND_EN_RESAMPLE_PHADC_DISABLE |
Disable the phase resampling |
0x0 |
|
|
FRONTEND_EN_RESAMPLE_PHADC_ENABLE |
Enable the phase resampling |
0x1* |
3:0 |
FRONTEND_DIV_PHADC |
FRONTEND_DIV_PHADC_DEFAULT |
|
0x0* |