SENSOR_CFG

Bit Field

Read/Write

Field Name

Description

24

RW

CLK_SEL

Clock source selection

20

RW

SRC_SEL

Sample source selection

13

RW

DLY_EN

Delay state enable

12

RW

DLY_DIV_EN

Delay divider selection

9:0

RW

DLY

Absolute Value of main counter to trigger the change of delay state

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

24

CLK_SEL

SENSOR_CLK_STANDBY

Standby clock is used as sensor clock

0x0

SENSOR_CLK_SYSCLK_DIV

Divided SYSCLK is used as sensor clock

0x1*

20

SRC_SEL

SAR_ADC_SELECTED

SAR ADC sample selected

0x0*

PC_SELECTED

Pulse Counter sample selected

0x1

13

DLY_EN

DLY_NOT_USED

Delay state is not used

0x0

DLY_USED

Delay state is used

0x1*

12

DLY_DIV_EN

DLY_DIV_DISABLED

Delay runs at sensor clock

0x0*

DLY_DIV_ENABLED

Delay runs at sensor clock divided by 32

0x1

9:0

DLY

DLY_1

Number of SENSOR_CLK periods for "Delay": 1

0x0*

DLY_2

Number of SENSOR_CLK periods for "Delay": 2

0x1

DLY_256

Number of SENSOR_CLK periods for "Delay": 256

0xFF

DLY_1024

Number of SENSOR_CLK periods for "Delay": 1024

0x3FF