LSAD
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40001C00 - 0x40001C1C |
LSAD_DATA_TRIM_CH_* |
- |
(13:0) DATA |
0x0 |
14-bit LSAD conversion result |
0x40001C20 - 0x40001C3C |
LSAD_DATA_AUDIO_CH_* |
- |
(31:0) DATA |
0x0 |
14-bit LSAD conversion result (sign extended to 32 bits) |
0x40001C40 - 0x40001C5C |
LSAD_INPUT_SEL_* |
(6:4) POS_INPUT_SEL |
(6:4) POS_INPUT_SEL |
0x6 |
Positive input selection |
|
|
(2:0) NEG_INPUT_SEL |
(2:0) NEG_INPUT_SEL |
0x7 |
Negative input selection |
0x40001C60 |
LSAD_CFG |
(4) CONTINUOUS_MODE |
(4) CONTINUOUS_MODE |
0x0 |
LSAD continuously sampling the channel selected as interrupt source (LSAD_INT_CH_NUM) |
|
|
(3:0) FREQ |
(3:0) FREQ |
0x0 |
Defines the sampling frequency of the LSAD channels |
0x40001C64 |
LSAD_OFFSET |
(14:0) DATA |
(14:0) DATA |
0x0 |
15-bit LSAD signed offset |
0x40001C68 |
LSAD_INT_ENABLE |
(3:1) LSAD_INT_CH_NUM |
(3:1) LSAD_INT_CH_NUM |
0x0 |
Channel number triggering the LSAD interrupt |
|
|
(0) LSAD_INT_ENABLE |
(0) LSAD_INT_ENABLE |
0x0 |
The LSAD new sample ready interrupt mask |
0x40001C6C |
LSAD_MONITOR_CFG |
(23:16) ALARM_COUNT_VALUE |
(23:16) ALARM_COUNT_VALUE |
0x0 |
An Alarm Status bit is set and an interrupt generated when SUPPLY_COUNT_VALUE = ALARM_COUNT_VALUE |
|
|
(15:8) MONITOR_THRESHOLD |
(15:8) MONITOR_THRESHOLD |
0xB3 |
Low voltage detection threshold (7.8 mV steps) |
|
|
(2:0) MONITOR_SRC |
(2:0) MONITOR_SRC |
0x7 |
Selects the source channel to be monitored |
0x40001C70 |
LSAD_MONITOR_COUNT_VAL |
- |
(7:0) MONITOR_COUNT_VALUE |
0x0 |
Number of times the voltage has fallen below the monitor voltage threshold. The counter is reset when read. |
0x40001C74 |
LSAD_MONITOR_STATUS |
(12) MONITOR_ALARM_CLEAR |
- |
N/A |
Monitoring alarm status bit |
|
|
(9) LSAD_OVERRUN_CLEAR |
- |
N/A |
LSAD Overrun condition |
|
|
(8) LSAD_READY_CLEAR |
- |
N/A |
LSAD new sample Ready status bit |
|
|
- |
(4) MONITOR_ALARM_STAT |
0x0 |
Monitoring alarm status bit |
|
|
- |
(1) LSAD_OVERRUN_STAT |
0x0 |
LSAD Overrun condition |
|
|
- |
(0) LSAD_READY_STAT |
0x0 |
LSAD new sample Ready status bit |
0x40001C78 |
LSAD_PRE_SEL_INPUT |
(14:12) LSAD_PRE_SEL_IN3 |
(14:12) LSAD_PRE_SEL_IN3 |
0x0 |
LSAD input pre-selection |
|
|
(10:8) LSAD_PRE_SEL_IN2 |
(10:8) LSAD_PRE_SEL_IN2 |
0x0 |
LSAD input pre-selection |
|
|
(6:4) LSAD_PRE_SEL_IN1 |
(6:4) LSAD_PRE_SEL_IN1 |
0x0 |
LSAD input pre-selection |
|
|
(2:0) LSAD_PRE_SEL_IN0 |
(2:0) LSAD_PRE_SEL_IN0 |
0x0 |
LSAD input pre-selection |
0x40001C7C |
LSAD_DUTY |
(15:14) CH7_DUTY_CFG |
(15:14) CH7_DUTY_CFG |
0x0 |
Input to channel 7 duty config |
|
|
(13:12) CH6_DUTY_CFG |
(13:12) CH6_DUTY_CFG |
0x0 |
Input to channel 6 duty config |
|
|
(11:10) CH5_DUTY_CFG |
(11:10) CH5_DUTY_CFG |
0x0 |
Input to channel 5 duty config |
|
|
(9:8) CH4_DUTY_CFG |
(9:8) CH4_DUTY_CFG |
0x0 |
Input to channel 4 duty config |
|
|
(7:6) CH3_DUTY_CFG |
(7:6) CH3_DUTY_CFG |
0x0 |
Input to channel 3 duty config |
|
|
(5:4) CH2_DUTY_CFG |
(5:4) CH2_DUTY_CFG |
0x0 |
Input to channel 2 duty config |
|
|
(3:2) CH1_DUTY_CFG |
(3:2) CH1_DUTY_CFG |
0x0 |
Input to channel 1 duty config |
|
|
(1:0) CH0_DUTY_CFG |
(1:0) CH0_DUTY_CFG |
0x0 |
Input to channel 0 duty config |
0x40001CFC |
LSAD_ID_NUM |
- |
(15:8) MAJOR_REVISION |
0x1 |
LSAD Major Revision number |
|
|
- |
(7:0) MINOR_REVISION |
0x0 |
LSAD Minor Revision number |