BBIF_CTRL
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
9:4 |
RW |
CLK_SEL |
Configure the internal baseband controller clock divider in order to provide a 1MHz reference clock |
1 |
RW |
WAKEUP_REQ |
External wake up request used to sort-out sleep modes |
0 |
RW |
CLK_ENABLE |
Enable the baseband controller clocks generation |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
9:4 |
CLK_SEL |
BBCLK_DIVIDER_6 |
Divide the BBCLK by 6 (minimum authorized value) |
0x6 |
|
|
BBCLK_DIVIDER_8 |
Divide the BBCLK by 8 |
0x8* |
|
|
BBCLK_DIVIDER_12 |
Divide the BBCLK by 12 |
0xC |
|
|
BBCLK_DIVIDER_16 |
Divide the BBCLK by 16 |
0x10 |
|
|
BBCLK_DIVIDER_24 |
Divide the BBCLK by 24 (maximum authorized value) |
0x18 |
1 |
WAKEUP_REQ |
BB_DEEP_SLEEP |
Keep the baseband controller in deep sleep mode |
0x0* |
|
|
BB_WAKEUP |
Wake up the baseband controller and keep it active |
0x1 |
0 |
CLK_ENABLE |
BB_CLK_DISABLE |
Baseband controller clocks are gated |
0x0* |
|
|
BB_CLK_ENABLE |
Baseband controller clocks are generated |
0x1 |