RF_XTAL_CTRL

Bit Field

Read/Write

Field Name

Description

31:28

RW

XTAL_CTRL_XO_THR_HIGH

High threshold for XTAL trimming

27:24

RW

XTAL_CTRL_XO_THR_LOW

Low threshold for XTAL trimming

23:22

RW

XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

Value of after_startup_curr_sel when level is higher than xo_thr_high

21:20

RW

XTAL_CTRL_XO_A_S_CURR_SEL_LOW

Value of after_startup_curr_sel when level is lower than xo_thr_low

19

RW

XTAL_CTRL_LOW_CLK_READY_TH_EN

clk_ready threshold

18

RW

XTAL_CTRL_XTAL_CTRL_BYPASS

Bypass the XTAL control algorithm

17

RW

XTAL_CTRL_DIG_CLK_IN_SEL

Clock selection for the digital block

16

RW

XTAL_CTRL_XO_EN_B_REG

XTAL oscillator enable

15:14

RW

XTAL_CTRL_XTAL_CKDIV

XTAL trimming speed

13

RW

XTAL_CTRL_CLK_OUT_EN_B

Output clock to go to main IP

12

RW

XTAL_CTRL_REG_VALUE_SEL

Control bits of xtal_reg

11:10

RW

XTAL_CTRL_AFTERSTARTUP_CURR_SEL

Selection of the current before amplitude stabilization but after starting-up in active transistors of the core oscillator

9:8

RW

XTAL_CTRL_STARTUP_CURR_SEL

Selection of the starting-up current in active transistors of the core oscillator

7

RW

XTAL_CTRL_INV_CLK_DIG

Invert clock on clk_dig output

6

RW

XTAL_CTRL_INV_CLK_PLL

Invert clock on clk_pll output

5

RW

XTAL_CTRL_FORCE_CLK_READY

Force output clocks on clk_pll, clk_dig and clk_out

4

RW

XTAL_CTRL_CLK_DIG_EN_B

Disable the output clock to go to digital (clk_dig output stay low)

3

RW

XTAL_CTRL_BUFF_EN_B

XTAL buffer disabling

2

RW

XTAL_CTRL_HP_MODE

Bias current increase in the clock buffer

1

RW

XTAL_CTRL_LP_MODE

Bias current decrease in the clock buffer

0

RW

XTAL_CTRL_EXT_CLK_MODE

Use XTAL pads as external clock input

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

31:28

XTAL_CTRL_XO_THR_HIGH

XTAL_CTRL_XO_THR_HIGH_DEFAULT

0xC*

27:24

XTAL_CTRL_XO_THR_LOW

XTAL_CTRL_XO_THR_LOW_DEFAULT

0x3*

23:22

XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

XTAL_CTRL_XO_A_S_CURR_SEL_HIGH_DEFAULT

0x2*

21:20

XTAL_CTRL_XO_A_S_CURR_SEL_LOW

XTAL_CTRL_XO_A_S_CURR_SEL_LOW_DEFAULT

0x0*

19

XTAL_CTRL_LOW_CLK_READY_TH_EN

XTAL_CTRL_LOW_CLK_READY_TH_EN_NOMINAL

The clk_ready threshold is nominal

0x0*

XTAL_CTRL_LOW_CLK_READY_TH_EN_LOW

The clk_ready threshold is set to a lower value

0x1

18

XTAL_CTRL_XTAL_CTRL_BYPASS

XTAL_CTRL_XTAL_CTRL_BYPASS_DISABLE

Don't bypass the Xtal control algorithm

0x0*

XTAL_CTRL_XTAL_CTRL_BYPASS_ENABLE

Bypass the Xtal control algorithm

0x1

17

XTAL_CTRL_DIG_CLK_IN_SEL

XTAL_CTRL_DIG_CLK_IN_SEL_XTAL

Select the internal xtal

0x0*

XTAL_CTRL_DIG_CLK_IN_SEL_CLK_IN

Select the clk_in_dig signal

0x1

16

XTAL_CTRL_XO_EN_B_REG

XTAL_CTRL_ENABLE_OSCILLATOR

Xtal oscillator enable

0x0

XTAL_CTRL_DISABLE_OSCILLATOR

Xtal oscillator disable

0x1*

15:14

XTAL_CTRL_XTAL_CKDIV

XTAL_CTRL_XTAL_CKDIV_0

43 us

0x0*

XTAL_CTRL_XTAL_CKDIV_1

85 us

0x1

XTAL_CTRL_XTAL_CKDIV_2

171 us

0x2

XTAL_CTRL_XTAL_CKDIV_3

341 us

0x3

13

XTAL_CTRL_CLK_OUT_EN_B

XTAL_CTRL_CLK_OUT_EN_B_ENABLE

Enable the output clock to go to main IP

0x0*

XTAL_CTRL_CLK_OUT_EN_B_DISABLE

Disable the output clock to go to main IP (clk_out output stay low)

0x1

12

XTAL_CTRL_REG_VALUE_SEL

XTAL_CTRL_REG_VALUE_SEL_EXTERNAL

Main ctrl signals are used instead of corresponding ctrl signal or some control bits of xtal_reg

0x0*

XTAL_CTRL_REG_VALUE_SEL_INTERNAL

Corresponding ctrl signal and some control bits of xtal_reg are used instead of main ctrl signals.

0x1

11:10

XTAL_CTRL_AFTERSTARTUP_CURR_SEL

XTAL_CTRL_AFTERSTARTUP_CURR_SEL_0

0.15 mA

0x0

XTAL_CTRL_AFTERSTARTUP_CURR_SEL_1

0.24 mA

0x1*

XTAL_CTRL_AFTERSTARTUP_CURR_SEL_2

0.40 mA

0x2

XTAL_CTRL_AFTERSTARTUP_CURR_SEL_3

0.61 mA

0x3

9:8

XTAL_CTRL_STARTUP_CURR_SEL

XTAL_CTRL_STARTUP_CURR_SEL_0

0.41 mA

0x0

XTAL_CTRL_STARTUP_CURR_SEL_1

0.59 mA

0x1*

XTAL_CTRL_STARTUP_CURR_SEL_2

0.88 mA

0x2

XTAL_CTRL_STARTUP_CURR_SEL_3

1.24 mA

0x3

7

XTAL_CTRL_INV_CLK_DIG

XTAL_CTRL_INV_CLK_DIG_DISABLE

Don't invert clock on clk_dig output

0x0*

XTAL_CTRL_INV_CLK_DIG_ENABLE

Invert clock on clk_dig output

0x1

6

XTAL_CTRL_INV_CLK_PLL

XTAL_CTRL_INV_CLK_PLL_DISABLE

Don't invert clock on clk_pll output

0x0*

XTAL_CTRL_INV_CLK_PLL_ENABLE

Invert clock on clk_pll output

0x1

5

XTAL_CTRL_FORCE_CLK_READY

XTAL_CTRL_FORCE_CLK_READY_DISABLE

Don't force output clocks on clk_pll, clk_dig and clk_out

0x0*

XTAL_CTRL_FORCE_CLK_READY_ENABLE

Force output clocks on clk_pll, clk_dig and clk_out and bypass the xtal internal clock detector

0x1

4

XTAL_CTRL_CLK_DIG_EN_B

XTAL_CTRL_CLK_DIG_EN_B_DISABLE

Enable the output clock to go to digital

0x0*

XTAL_CTRL_CLK_DIG_EN_B_ENABLE

Disable the output clock to go to digital (clk_dig output stay low)

0x1

3

XTAL_CTRL_BUFF_EN_B

XTAL_CTRL_BUFF_EN_B_DISABLE

The xtal buffer is enabled

0x0*

XTAL_CTRL_BUFF_EN_B_ENABLE

The xtal buffer is disabled

0x1

2

XTAL_CTRL_HP_MODE

XTAL_CTRL_HP_MODE_NOMINAL

The bias current in the clock buffer is nominal

0x0*

XTAL_CTRL_HP_MODE_HIGH

The bias current in the clock buffer is increased

0x1

1

XTAL_CTRL_LP_MODE

XTAL_CTRL_LP_MODE_NOMINAL

The bias current in the clock buffer is nominal

0x0*

XTAL_CTRL_LP_MODE_HIGH

The bias current in the clock buffer is reduced compared to normal operatio

0x1

0

XTAL_CTRL_EXT_CLK_MODE

XTAL_CTRL_EXT_CLK_MODE_DISABLE

Don not use xtal_p (and eventually xtal_n) as external clock input(s)

0x0*

XTAL_CTRL_EXT_CLK_MODE_ENABLE

Use xtal_p (and eventually xtal_n) as external clock input(s)

0x1