CLK_DIV_CFG2

Bit Field

Read/Write

Field Name

Description

20

RW

PWM_CLK_SRC

PWM clock source

16

RW

USRCLK_SRC_SEL

USR clock source selection

11:0

RW

USRCLK_PRESCALE

Prescale value for the USR clock (1 to 4096 in steps of 1)

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

20

PWM_CLK_SRC

PWM_SRC_SYSCLK

PWM clock based on system clock

0x0*

PWM_SRC_SLOWCLK

PWM clock based on SLOW clock

0x1

16

USRCLK_SRC_SEL

USRCLK_SRC_SYSCLK

User clock based on system clock

0x0*

USRCLK_SRC_RFCLK

User clock based on RF clock

0x1

11:0

USRCLK_PRESCALE

USRCLK_PRESCALE_1

Divide by 1

0x0*

USRCLK_PRESCALE_2

Divide by 2

0x1

USRCLK_PRESCALE_3

Divide by 3

0x2

USRCLK_PRESCALE_4095

Divide by 4095

0xFFE

USRCLK_PRESCALE_4096

Divide by 4096

0xFFF