SYSCTRL_CC_DCU_EN0

Bit Field

Read/Write

Field Name

Description

31

R

CC_DCU_EN_ICV_GP

Always On ICV governed dcu_en0 general purpose bits

30:28

R

CC_DCU_EN_ICV_EH

Always On ICV governed energy harversting signature. Majority of the bis must be set to confirm the state.

27:25

R

CC_DCU_EN_ICV_PRDSTATE

Always On ICV governed production state identifier

24:22

R

CC_DCU_EN_ICV_TCTRL_ACC

Always On ICV governed test control configuration access control. Majority of the bits must be set to enable the feature

21:19

R

CC_DCU_EN_ICV_TRIM_ACC

Always On ICV governed MNVR and chip trim access control. Majority of the bits must be set to enable the feature

18:16

R

CC_DCU_EN_ICV_NVM_ACC

Always On ICV governed NVM access control. Majority of the bits must be set to enable the feature

15:13

R

CC_DCU_EN_ICV_SEC_RST

Always On ICV governed secure reset enable. If any of these bits are set and the part is in SE state, the cc312_top is reset

12:10

R

CC_DCU_EN_ICV_SPINDEN

Always On ICV governed CM33 secure non-intrusive debug enable control. Majority of the bits must be set to enable the feature

9:7

R

CC_DCU_EN_ICV_SPIDEN

Always On ICV governed CM33 secure intrusive debug enable control. Majority of the bits must be set to enable the feature

6:4

R

CC_DCU_EN_ICV_NIDEN

Always On ICV governed CM33 non-intrusive debug enable control. Majority of the bits must be set to enable the feature

3:1

R

CC_DCU_EN_ICV_DBGEN

Always On ICV governed CM33 debug enable control. Majority of the bits must be set to enable the feature

0

R

CC_DCU_EN_ICV_SEC_RST_MASK

Always On ICV governed secure reset mask used in FW

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

0

CC_DCU_EN_ICV_SEC_RST_MASK

CC_SECURE_RST_FW_EN

The FW does not mask the secure debug reset bits

0x0*

CC_SECURE_RST_FW_DIS

The FW masks the secure debug reset bits, no reset can be issued

0x1