UART Interface
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40000F00 |
UART0_CFG |
(21) TX_DMA_ENABLE |
(21) TX_DMA_ENABLE |
0x0 |
Enable/disable the TX DMA request |
|
|
(20) RX_DMA_ENABLE |
(20) RX_DMA_ENABLE |
0x0 |
Enable/disable the RX DMA request |
|
|
(19) TX_END_INT_ENABLE |
(19) TX_END_INT_ENABLE |
0x0 |
Enable/disable the TX end interrupt |
|
|
(18) TX_START_INT_ENABLE |
(18) TX_START_INT_ENABLE |
0x0 |
Enable/disable the TX start interrupt |
|
|
(17) RX_INT_ENABLE |
(17) RX_INT_ENABLE |
0x0 |
Enable/disable the RX interrupt |
|
|
(16) OVERRUN_INT_ENABLE |
(16) OVERRUN_INT_ENABLE |
0x0 |
Enable/disable the overrun interrupt |
|
|
(15:0) CNT_STEP |
(15:0) CNT_STEP |
0x0 |
Counter step size that configures the baud rate |
0x40000F04 |
UART0_CTRL |
- |
(8) ENABLE_STATUS |
0x0 |
UART enable status |
|
|
(2) RESET |
- |
N/A |
Reset the UART interface |
|
|
(1) DISABLE |
- |
N/A |
Disable the UART interface |
|
|
(0) ENABLE |
- |
N/A |
Enable the UART interface |
0x40000F08 |
UART0_STATUS |
- |
(12) TX_BUSY |
0x0 |
Indicate that a TX transaction is ongoing |
|
|
- |
(11) RX_BUSY |
0x0 |
Indicate that a RX transaction is ongoing |
|
|
- |
(10) TX_REQ |
0x1 |
Indicate that a TX data can be written |
|
|
- |
(9) RX_REQ |
0x0 |
Indicate that a RX data can be read |
|
|
- |
(8) OVERRUN |
0x0 |
Indicate that an overrun occurred when receiving data |
|
|
(0) OVERRUN_CLEAR |
- |
N/A |
Clear the overrun status flag |
0x40000F0C |
UART0_TX_DATA |
(7:0) TX_DATA |
(7:0) TX_DATA |
0x0 |
Transmitted data |
0x40000F10 |
UART0_RX_DATA |
- |
(7:0) RX_DATA |
0x0 |
Received data |
0x40000FFC |
UART0_ID_NUM |
- |
(19:16) UART_NUMBER |
0x0 |
UART Instance number |
|
|
- |
(15:8) UART_MAJOR_REVISION |
0x1 |
UART Major Revision number |
|
|
- |
(7:0) UART_MINOR_REVISION |
0x0 |
UART Minor Revision number |