SYSCTRL_CC_FEATURES_CTRL
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
30 |
R |
CC_OEM_SEC_RST_ALL |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SEC_RST operation |
29 |
R |
CC_OEM_SPINDEN_ALL |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SPINDEN operation |
28 |
R |
CC_OEM_SPIDEN_ALL |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SPIDEN operation |
27 |
R |
CC_OEM_NIDEN_ALL |
Always On block OEM governed DCU_EN bits fault status allocated for enabling NIDEN operation |
26 |
R |
CC_OEM_DBGEN_ALL |
Always On block OEM governed DCU_EN bits fault status allocated for enabling DBGEN operation |
25 |
R |
CC_ENERGY_HARVESTING_ALL |
Always On block DCU_EN bits fault status allocated for enabling ENERGY_HARVESTING operation |
24 |
R |
CC_PROD_STATUS_ALL |
Always On block DCU_EN bits fault status allocated for enabling PROD_STATUS operation |
23 |
R |
CC_TCTRL_ACC_ALL |
Always On block DCU_EN bits fault status allocated for enabling TCTRL_ACC operation |
22 |
R |
CC_TRIM_ACC_ALL |
Always On block DCU_EN bits fault status allocated for enabling TRIM_ACC operation |
21 |
R |
CC_NVM_ACC_ALL |
Always On block DCU_EN bits fault status allocated for enabling NVM_ACC operation |
20 |
R |
CC_ICV_SEC_RST_ALL |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SEC_RST operation |
19 |
R |
CC_ICV_SPINDEN_ALL |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SPINDEN operation |
18 |
R |
CC_ICV_SPIDEN_ALL |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SPIDEN operation |
17 |
R |
CC_ICV_NIDEN_ALL |
Always On block ICV governed DCU_EN bits fault status allocated for enabling NIDEN operation |
16 |
R |
CC_ICV_DBGEN_ALL |
Always On block ICV governed DCU_EN bits fault status allocated for enabling DBGEN operation |
13 |
R |
CC_OEM_SPINDEN |
Always On block OEM SPINDEN status as the result of the equality check and production state confirmation |
12 |
R |
CC_OEM_SPIDEN |
Always On block OEM SPIDEN status as the result of the equality check and production state confirmation |
11 |
R |
CC_OEM_NIDEN |
Always On block OEM NIDEN status as the result of the equality check and production state confirmation |
10 |
R |
CC_OEM_DBGEN |
Always On block OEM DBGEN status as the result of the equality check and production state confirmation |
9 |
R |
CC_ENERGY_HARVESTING |
Always On block Energy Harvesting status as the result of equality check |
8 |
R |
CC_PROD_STATUS |
Always On block Production Status as the result of equality check |
7 |
R |
CC_TCTRL_ACC |
Always On block TCTRL_ACC status as the result of the equality check and production state confirmation |
6 |
R |
CC_TRIM_ACC |
Always On block TRIM_ACC status as the result of the equality check and production state confirmation |
5 |
R |
CC_NVM_ACC |
Always On block NVM_ACC status as the result of the equality check and production state confirmation |
4 |
R |
CC_SEC_RST |
Always On block ICV or OEM SEC_RST status as the result of any bit being set. |
3 |
R |
CC_ICV_SPINDEN |
Always On block ICV SPINDEN status as the result of the equality check and production state confirmation |
2 |
R |
CC_ICV_SPIDEN |
Always On block ICV SPIDEN status as the result of the equality check and production state confirmation |
1 |
R |
CC_ICV_NIDEN |
Always On block ICV NIDEN status as the result of the equality check and production state confirmation |
0 |
R |
CC_ICV_DBGEN |
Always On block ICV DBGEN status as the result of the equality check and production state confirmation |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
30 |
CC_OEM_SEC_RST_ALL |
CC_OEM_SEC_RST_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_OEM_SEC_RST_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
29 |
CC_OEM_SPINDEN_ALL |
CC_OEM_SPINDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_OEM_SPINDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
28 |
CC_OEM_SPIDEN_ALL |
CC_OEM_SPIDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_OEM_SPIDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
27 |
CC_OEM_NIDEN_ALL |
CC_OEM_NIDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_OEM_NIDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
26 |
CC_OEM_DBGEN_ALL |
CC_OEM_DBGEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_OEM_DBGEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
25 |
CC_ENERGY_HARVESTING_ALL |
CC_ENERGY_HARVESTING_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ENERGY_HARVESTING_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
24 |
CC_PROD_STATUS_ALL |
CC_PROD_STATUS_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_PROD_STATUS_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
23 |
CC_TCTRL_ACC_ALL |
CC_TCTRL_ACC_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_TCTRL_ACC_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
22 |
CC_TRIM_ACC_ALL |
CC_TRIM_ACC_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_TRIM_ACC_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
21 |
CC_NVM_ACC_ALL |
CC_NVM_ACC_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_NVM_ACC_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
20 |
CC_ICV_SEC_RST_ALL |
CC_ICV_SEC_RST_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ICV_SEC_RST_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
19 |
CC_ICV_SPINDEN_ALL |
CC_ICV_SPINDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ICV_SPINDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
18 |
CC_ICV_SPIDEN_ALL |
CC_ICV_SPIDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ICV_SPIDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
17 |
CC_ICV_NIDEN_ALL |
CC_ICV_NIDEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ICV_NIDEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
16 |
CC_ICV_DBGEN_ALL |
CC_ICV_DBGEN_DCUEN_MATCH |
The DCU_EN bits allocated for the feature are all equal |
0x0* |
|
|
CC_ICV_DBGEN_DCUEN_MISMATCH |
The DCU_EN bits allocated for the feature have mismatch |
0x1 |
13 |
CC_OEM_SPINDEN |
CC_OEM_SPINDEN_INACTIVE |
Secure non-invasive CM33 debug disabled by OEM |
0x0* |
|
|
CC_OEM_SPINDEN_ACTIVE |
Secure non-invasive CM33 debug enabled by OEM, all bits set |
0x1 |
12 |
CC_OEM_SPIDEN |
CC_OEM_SPIDEN_INACTIVE |
Secure invasive CM33 debug disabled by OEM |
0x0* |
|
|
CC_OEM_SPIDEN_ACTIVE |
Secure invasive CM33 debug enabled by OEM, all bits set |
0x1 |
11 |
CC_OEM_NIDEN |
CC_OEM_NIDEN_INACTIVE |
Non-invasive CM33 debug disabled by OEM |
0x0* |
|
|
CC_OEM_NIDEN_ACTIVE |
Non-invasive CM33 debug enabled by OEM, all bits set |
0x1 |
10 |
CC_OEM_DBGEN |
CC_OEM_DBGEN_INACTIVE |
CM33 debug disabled by OEM |
0x0* |
|
|
CC_OEM_DBGEN_ACTIVE |
CM33 debug enabled by OEM, all bits set |
0x1 |
9 |
CC_ENERGY_HARVESTING |
CC_ENERGY_HARVESTING_INACTIVE |
Energy harvesting is inactive. |
0x0* |
|
|
CC_ENERGY_HARVESTING_ACTIVE |
Energy harvesting is active, all bits set |
0x1 |
8 |
CC_PROD_STATUS |
CC_PROD_NOT_DONE |
Production is not done. |
0x0* |
|
|
CC_PROD_DONE |
Production screening done, all bits set |
0x1 |
7 |
CC_TCTRL_ACC |
CC_TCTRL_ACC_INACTIVE |
Test_ctrl register access disabled |
0x0* |
|
|
CC_TCTRL_ACC_ACTIVE |
Test_ctrl register access enabled, all bits set |
0x1 |
6 |
CC_TRIM_ACC |
CC_TRIM_ACC_INACTIVE |
MNVR and chip trim access disabled |
0x0* |
|
|
CC_TRIM_ACC_ACTIVE |
MNVR and chip trim access enabled, all bits set |
0x1 |
5 |
CC_NVM_ACC |
CC_NVM_ACC_INACTIVE |
NVM access limited |
0x0* |
|
|
CC_NVM_ACC_ACTIVE |
NVM access available for ERASE and WRITE command, all bits set |
0x1 |
4 |
CC_SEC_RST |
CC_SEC_RST_INACTIVE |
None of the bits are set, the feature is deactivated by ICV or OEM |
0x0* |
|
|
CC_SEC_RST_ACTIVE |
Some of the bits are set by ICV or OEM to activate the feature |
0x1 |
3 |
CC_ICV_SPINDEN |
CC_ICV_SPINDEN_INACTIVE |
Secure non-invasive CM33 debug disabled by ICV |
0x0* |
|
|
CC_ICV_SPINDEN_ACTIVE |
Secure non-invasive CM33 debug enabled by ICV, all bits set |
0x1 |
2 |
CC_ICV_SPIDEN |
CC_ICV_SPIDEN_INACTIVE |
Secure invasive CM33 debug disabled by ICV |
0x0* |
|
|
CC_ICV_SPIDEN_ACTIVE |
Secure invasive CM33 debug enabled by ICV, all bits set |
0x1 |
1 |
CC_ICV_NIDEN |
CC_ICV_NIDEN_INACTIVE |
Non-invasive CM33 debug disabled by ICV |
0x0* |
|
|
CC_ICV_NIDEN_ACTIVE |
Non-invasive CM33 debug enabled by ICV, all bits set |
0x1 |
0 |
CC_ICV_DBGEN |
CC_ICV_DBGEN_INACTIVE |
CM33 debug disabled by ICV |
0x0* |
|
|
CC_ICV_DBGEN_ACTIVE |
CM33 debug enabled by ICV, all bits set |
0x1 |