DMA_CTRL
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
13 |
RW |
INT_CNT_TRIGGER_ENABLE |
Enable waiting on a trigger when an interrupt counter event occurs |
12:8 |
RW |
TRIGGER_SOURCE |
Selects which event triggers this DMA channel when triggering is enabled |
6 |
RW |
INT_CNT_ADDR_WRAP_ENABLE |
Enable source or destination (depending on SRC_DEST_TRANS_LENGTH_SEL) address wrapping when an interrupt counter event occurs |
5 |
RW |
CLEAR_BUFFER_WHEN_WRAPPING |
Clear buffer during address wrapping |
4 |
W |
BUFFER_CLEAR |
Clear source buffer |
3 |
W |
CNTS_CLEAR |
Clear counters |
2:0 |
RW |
MODE_ENABLE |
Enable mode of operation of the DMA Channel |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
13 |
INT_CNT_TRIGGER_ENABLE |
DMA_INT_CNT_TRIGGER_DISABLE |
The DMA channel does not pause when an interrupt counter event occurs |
0x0* |
|
|
DMA_INT_CNT_TRIGGER_ENABLE |
The DMA channel pauses when an interrupt counter event occurs and waits for a trigger source event to continue |
0x1 |
12:8 |
TRIGGER_SOURCE |
DMA_CH0_COMPLETED |
This DMA channel is triggered when CH0_COMPLETED occurs |
0x0* |
|
|
DMA_CH1_COMPLETED |
This DMA channel is triggered when CH1_COMPLETED occurs |
0x1 |
|
|
DMA_CH2_COMPLETED |
This DMA channel is triggered when CH2_COMPLETED occurs |
0x2 |
|
|
DMA_CH3_COMPLETED |
This DMA channel is triggered when CH3_COMPLETED occurs |
0x3 |
|
|
DMA_SENSOR |
This DMA channel is triggered when SENSOR occurs |
0x4 |
|
|
DMA_LIN_RX |
This DMA channel is triggered when LIN_RX occurs |
0x5 |
|
|
DMA_SAR |
This DMA channel is triggered when SAR occurs |
0x6 |
|
|
DMA_TIMER0 |
This DMA channel is triggered when TIMER0 occurs |
0x7 |
|
|
DMA_TIMER1 |
This DMA channel is triggered when TIMER1 occurs |
0x8 |
|
|
DMA_TIMER2 |
This DMA channel is triggered when TIMER2 occurs |
0x9 |
|
|
DMA_TIMER3 |
This DMA channel is triggered when TIMER3 occurs |
0xA |
|
|
DMA_TRIGGER_NOT_USED_11 |
This DMA channel is triggered when TRIGGER_NOT_USED_11 occurs |
0xB |
|
|
DMA_TRIGGER_NOT_USED_12 |
This DMA channel is triggered when TRIGGER_NOT_USED_12 occurs |
0xC |
|
|
DMA_TRIGGER_NOT_USED_13 |
This DMA channel is triggered when TRIGGER_NOT_USED_13 occurs |
0xD |
|
|
DMA_TRIGGER_NOT_USED_14 |
This DMA channel is triggered when TRIGGER_NOT_USED_14 occurs |
0xE |
|
|
DMA_TRIGGER_NOT_USED_15 |
This DMA channel is triggered when TRIGGER_NOT_USED_15 occurs |
0xF |
|
|
DMA_TRIGGER_NOT_USED_16 |
This DMA channel is triggered when TRIGGER_NOT_USED_16 occurs |
0x10 |
|
|
DMA_TRIGGER_NOT_USED_17 |
This DMA channel is triggered when TRIGGER_NOT_USED_17 occurs |
0x11 |
|
|
DMA_TRIGGER_NOT_USED_18 |
This DMA channel is triggered when TRIGGER_NOT_USED_18 occurs |
0x12 |
|
|
DMA_TRIGGER_NOT_USED_19 |
This DMA channel is triggered when TRIGGER_NOT_USED_19 occurs |
0x13 |
|
|
DMA_TRIGGER_NOT_USED_20 |
This DMA channel is triggered when TRIGGER_NOT_USED_20 occurs |
0x14 |
|
|
DMA_TRIGGER_NOT_USED_21 |
This DMA channel is triggered when TRIGGER_NOT_USED_21 occurs |
0x15 |
|
|
DMA_TRIGGER_NOT_USED_22 |
This DMA channel is triggered when TRIGGER_NOT_USED_22 occurs |
0x16 |
|
|
DMA_TRIGGER_NOT_USED_23 |
This DMA channel is triggered when TRIGGER_NOT_USED_23 occurs |
0x17 |
|
|
DMA_TRIGGER_NOT_USED_24 |
This DMA channel is triggered when TRIGGER_NOT_USED_24 occurs |
0x18 |
|
|
DMA_TRIGGER_NOT_USED_25 |
This DMA channel is triggered when TRIGGER_NOT_USED_25 occurs |
0x19 |
|
|
DMA_TRIGGER_NOT_USED_26 |
This DMA channel is triggered when TRIGGER_NOT_USED_26 occurs |
0x1A |
|
|
DMA_TRIGGER_NOT_USED_27 |
This DMA channel is triggered when TRIGGER_NOT_USED_27 occurs |
0x1B |
|
|
DMA_TRIGGER_NOT_USED_28 |
This DMA channel is triggered when TRIGGER_NOT_USED_28 occurs |
0x1C |
|
|
DMA_TRIGGER_NOT_USED_29 |
This DMA channel is triggered when TRIGGER_NOT_USED_29 occurs |
0x1D |
|
|
DMA_TRIGGER_NOT_USED_30 |
This DMA channel is triggered when TRIGGER_NOT_USED_30 occurs |
0x1E |
|
|
DMA_TRIGGER_NOT_USED_31 |
This DMA channel is triggered when TRIGGER_NOT_USED_31 occurs |
0x1F |
6 |
INT_CNT_ADDR_WRAP_ENABLE |
DMA_INT_CNT_ADDR_WRAP_DISABLE |
Source address and destination addresses are wrapped normally |
0x0* |
|
|
DMA_INT_CNT_ADDR_WRAP_ENABLE |
When the interrupt counter is reached, source or destination address is wrapped depending on SRC_DEST_TRANS_LENGTH_SEL |
0x1 |
5 |
CLEAR_BUFFER_WHEN_WRAPPING |
DMA_KEEP_BUFFER_WHEN_WRAPPING |
Buffer contents are not cleared during address wrapping |
0x0* |
|
|
DMA_CLEAR_BUFFER_WHEN_WRAPPING |
Buffer contents are cleared during address wrapping |
0x1 |
4 |
BUFFER_CLEAR |
DMA_CLEAR_BUFFER |
Clears the DMA source buffered data |
0x1 |
3 |
CNTS_CLEAR |
DMA_CLEAR_CNTS |
Clears the DMA counters |
0x1 |
2:0 |
MODE_ENABLE |
DMA_DISABLE |
Disable DMA channel (channel waits on current READ or WRITE access to finish before the active bit is cleared) |
0x0* |
|
|
DMA_ENABLE |
Enable DMA channel and when completed disable |
0x1 |
|
|
DMA_ENABLE_WRAP |
Enable DMA channel and when completed, wrap addresses and disable |
0x2 |
|
|
DMA_ENABLE_WRAP_RESTART |
Enable DMA channel and when completed, wrap addresses and restart |
0x3 |
|
|
DMA_TRIGGER |
When source trigger occurs enable DMA channel, when completed disable |
0x4 |
|
|
DMA_TRIGGER_WRAP |
When source trigger occurs enable DMA channel, when completed wrap addresses and disable |
0x5 |
|
|
DMA_TRIGGER_WRAP_RESTART |
When source trigger occurs enable DMA channel, when completed wrap addresses and restart |
0x6 |
|
|
DMA_TRIGGER_WRAP_TRIGGER_RESTART |
When source trigger occurs enable DMA channel, when completed wrap addresses, and upon next trigger event restart |
0x7 |