Baseband Controller Registers
Register Name |
Register Description |
Address |
---|---|---|
Baseband control register |
0x40001900 |
|
BLE revision register |
0x40001904 |
|
Baseband configuration register (compilation options dependant) |
0x40001908 |
|
Interrupts control register 0 |
0x4000190C |
|
Interrupts status register 0 |
0x40001910 |
|
Interrupts raw status register 0 |
0x40001914 |
|
Interrupts control register 1 |
0x40001918 |
|
Interrupts status register 1 |
0x4000191C |
|
Interrupts acknowledgement register 1 |
0x40001920 |
|
Actif FIFO status register |
0x40001924 |
|
Rx descriptor pointer register |
0x40001928 |
|
Rx descriptor pointer register |
0x4000192C |
|
Deep sleep control register |
0x40001930 |
|
Deep sleep wakeup register |
0x40001934 |
|
Deep sleep status register |
0x40001938 |
|
Stabilization times |
0x4000193C |
|
Fine timer correction register |
0x40001940 |
|
Slot clock correction register |
0x40001944 |
|
Diagnostic ports control register |
0x40001950 |
|
Diagnostic ports status register |
0x40001954 |
|
Diagnostic ports upper limit |
0x40001958 |
|
Diagnostic ports lower limit |
0x4000195C |
|
Diagnostic ports errors register |
0x40001960 |
|
Software profiling register |
0x40001964 |
|
Principal control register for the radio interface |
0x40001970 |
|
Second control register for the radio interface |
0x40001974 |
|
Third control register for the radio interface |
0x40001978 |
|
Fourth control register for the radio interface |
0x4000197C |
|
Principal control register for the radio interface power up/down delays |
0x40001980 |
|
Second control register for the radio interface power up/down delays |
0x40001984 |
|
Third control register for the radio interface power up/down delays (only when LR is instantiated) |
0x40001988 |
|
Fourth control register for the radio interface power up/down delays (only when LR is instantiated) |
0x4000198C |
|
Principal control register for the radio interface timing compensation delays |
0x40001990 |
|
Second control register for the radio interface timing compensation delays |
0x40001994 |
|
Third control register for the radio interface timing compensation delays (only when LR is instantiated) |
0x40001998 |
|
Fourth control register for the radio interface timing compensation delays (only when LR is instantiated) |
0x4000199C |
|
First control register for the radio interface SPI pointers |
0x400019A0 |
|
Second control register for the radio interface SPI pointers |
0x400019A4 |
|
Third control register for the radio interface SPI pointers |
0x400019A8 |
|
Fourth control register for the radio interface SPI pointers |
0x400019AC |
|
AES-128 ciphering control register |
0x400019B0 |
|
AES encryption 128-bit key register (bits 31:0) |
0x400019B4 |
|
AES encryption 128-bit key register (bits 63:32) |
0x400019B8 |
|
AES encryption 128-bit key register (bits 95:64) |
0x400019BC |
|
AES encryption 128-bit key register (bits 127:96) |
0x400019C0 |
|
AES memory zone pointer |
0x400019C4 |
|
AES-CCM plain MIC value register in Tx |
0x400019C8 |
|
AES-CCM plain MIC value register in Rx |
0x400019CC |
|
RF testing and regulatory body support register |
0x400019D0 |
|
Number of transmitted packet during test modes |
0x400019D4 |
|
Number of correctly received packet during test modes |
0x400019D8 |
|
Timing generator control register |
0x400019E0 |
|
Fine timer control register |
0x400019E4 |
|
CLKN target value 1 |
0x400019E8 |
|
Half microsecond target value 1 |
0x400019EC |
|
CLKN target value 2 |
0x400019F0 |
|
Half microsecond target value 2 |
0x400019F4 |
|
Value of the 312.5us CLKN counter |
0x400019F8 |
|
Value of the current half us fine time reference counter |
0x400019FC |
|
Value of the 312.5us CLKN counter |
0x40001A00 |
|
Value of the CLKN counter when ble_start_int is generated |
0x40001A04 |
|
Value of the fine counter when ble_start_int is generated |
0x40001A08 |
|
Value of the CLKN counter when ble_end_int is generated |
0x40001A0C |
|
Value of the fine counter when ble_end_int is generated |
0x40001A10 |
|
Value of the CLKN counter when ble_skip_int is generated |
0x40001A14 |
|
Value of the fine counter when ble_skip_int is generated |
0x40001A18 |
|
Delay information register handling advertising event timers |
0x40001A20 |
|
Active scan mode control register |
0x40001A24 |
|
Devices in white list |
0x40001A30 |
|
Current pointer in use for the White List |
0x40001A34 |
|
RAL and List Search engines timeout delay in us |
0x40001A38 |
|
WLAN coexistence control register 0 |
0x40001A40 |
|
WLAN coexistence control register 1 |
0x40001A44 |
|
WLAN coexistence control register 2 |
0x40001A48 |
|
Priority control register 0 |
0x40001A4C |
|
Priority control register 1 |
0x40001A50 |
|
Priority control register 2 |
0x40001A54 |
|
Control of the Resolving Address List engine |
0x40001A60 |
|
Current pointer of the RAL structure |
0x40001A64 |
|
Register used by the local Resolving Address List engine |
0x40001A68 |
|
Register used by the peer Resolving Address List engine |
0x40001A6C |
|
AoA/AOD control register 0 (1us) |
0x40001A70 |
|
AoA/AOD control register 0 (2us) |
0x40001A74 |
|
AoA/AOD control register 1 (1us) |
0x40001A78 |
|
AoA/AOD control register 1 (2us) |
0x40001A7C |
|
Rx CTE descriptor current pointer |
0x40001A80 |
|
AoA/AOD antenna control register |
0x40001A84 |
|
AoA/AOD interface control register |
0x40001A88 |