RF_REG1B
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
31 |
RW |
PLL_BANK_EN_LOW_CHP_BIAS_TX |
Set the en_low_chp_bias bit in Tx mode (banked) |
30 |
RW |
PLL_BANK_EN_LOW_CHP_BIAS_RX |
Set the en_low_chp_bias bit in Rx mode (banked) |
29:28 |
RW |
PLL_BANK_PLL_FILTER_RES_TRIM_TX |
Modify the value of the loop filter resistor R2 when bit 5 is high in Tx mode (banked) |
27:24 |
RW |
PLL_BANK_IQ_PLL_0_TX |
Charge pump bias for Tx case (banked) |
22 |
RW |
PLL_BANK_LOW_DR_TX |
Enable low data-rate mode in Tx mode (banked) |
21:20 |
RW |
PLL_BANK_PLL_FILTER_RES_TRIM_RX |
Modify the value of the loop filter resistor R2 when bit 5 is high in Rx mode (banked) |
19:16 |
RW |
PLL_BANK_IQ_PLL_0_RX |
Charge pump bias for Rx (banked) |
15 |
RW |
ANACLK_USE_NEW_ANACK |
Use the new analog clock generator (banked) |
13:12 |
RW |
ANACLK_DIV_CK_RSSI |
Set the master clock divider for the RSSI clock (banked) |
11:10 |
RW |
ANACLK_DIV_CK_FILT |
Set the master clock divider for the channel filter clock (banked) |
9:8 |
RW |
ANACLK_DIV_CK_PHADC |
Set the master clock divider for the phase ADC clock (banked) |
7:4 |
RW |
ANACLK_DIV_RSSI |
Unsigned value that specifies the division factor for the clock controlling the RSSI (banked) |
3:0 |
RW |
ANACLK_DIV_FILT |
Unsigned value that specifies the division factor for the clock controlling the channel filter (banked) |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
31 |
PLL_BANK_EN_LOW_CHP_BIAS_TX |
PLL_BANK_EN_LOW_CHP_BIAS_TX_RESET |
In Tx mode EN_LOW_CHP_BIAS bit is reset |
0x0* |
|
|
PLL_BANK_EN_LOW_CHP_BIAS_TX_SET |
In Tx mode EN_LOW_CHP_BIAS bit is set |
0x1 |
30 |
PLL_BANK_EN_LOW_CHP_BIAS_RX |
PLL_BANK_EN_LOW_CHP_BIAS_RX_RESET |
In Rx mode EN_LOW_CHP_BIAS bit is reset |
0x0 |
|
|
PLL_BANK_EN_LOW_CHP_BIAS_RX_SET |
In Rx mode EN_LOW_CHP_BIAS bit is set |
0x1* |
29:28 |
PLL_BANK_PLL_FILTER_RES_TRIM_TX |
PLL_BANK_PLL_FILTER_RES_TRIM_TX_0 |
Normal resistor |
0x0 |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_TX_1 |
Normal resistor + 23% |
0x1 |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_TX_2 |
Normal resistor + 30% |
0x2 |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_TX_3 |
Normal resistor + 70% |
0x3* |
27:24 |
PLL_BANK_IQ_PLL_0_TX |
PLL_BANK_IQ_PLL_0_TX_DEFAULT |
|
0x4* |
22 |
PLL_BANK_LOW_DR_TX |
PLL_BANK_LOW_DR_TX_DISABLE |
Tx works not in low data rate |
0x0* |
|
|
PLL_BANK_LOW_DR_TX_ENABLE |
Tx works in low data rate |
0x1 |
21:20 |
PLL_BANK_PLL_FILTER_RES_TRIM_RX |
PLL_BANK_PLL_FILTER_RES_TRIM_RX_0 |
Normal resistor |
0x0* |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_RX_1 |
Normal resistor + 23% |
0x1 |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_RX_2 |
Normal resistor + 30% |
0x2 |
|
|
PLL_BANK_PLL_FILTER_RES_TRIM_RX_3 |
Normal resistor + 70% |
0x3 |
19:16 |
PLL_BANK_IQ_PLL_0_RX |
PLL_BANK_IQ_PLL_0_RX_DEFAULT |
|
0xB* |
15 |
ANACLK_USE_NEW_ANACK |
ANACLK_USE_NEW_ANACK_DISABLE |
Do not use the analog clock generator |
0x0* |
|
|
ANACLK_USE_NEW_ANACK_ENABLE |
Use the analog clock generator |
0x1 |
13:12 |
ANACLK_DIV_CK_RSSI |
ANACLK_DIV_CK_RSSI_3 |
Division by 3 |
0x0* |
|
|
ANACLK_DIV_CK_RSSI_2 |
Division by 2 |
0x1 |
|
|
ANACLK_DIV_CK_RSSI_1 |
Division by 1 |
0x2 |
11:10 |
ANACLK_DIV_CK_FILT |
ANACLK_DIV_CK_FILT_3 |
Division by 3 |
0x0* |
|
|
ANACLK_DIV_CK_FILT_2 |
Division by 2 |
0x1 |
|
|
ANACLK_DIV_CK_FILT_1 |
Division by 1 |
0x2 |
9:8 |
ANACLK_DIV_CK_PHADC |
ANACLK_DIV_CK_PHADC_3 |
Division by 3 |
0x0* |
|
|
ANACLK_DIV_CK_PHADC_2 |
Division by 2 |
0x1 |
|
|
ANACLK_DIV_CK_PHADC_1 |
Division by 1 |
0x2 |
7:4 |
ANACLK_DIV_RSSI |
ANACLK_DIV_RSSI_DEFAULT |
|
0x1* |
3:0 |
ANACLK_DIV_FILT |
ANACLK_DIV_FILT_DEFAULT |
|
0x5* |