Clock Generation
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40000100 |
CLK_SYS_CFG |
(19:16) EXTCLK_PRESCALE |
(19:16) EXTCLK_PRESCALE |
0x0 |
Prescale value for the input clock EXTCLK (1 to 16 in steps of 1) |
|
|
(11:8) SWCLK_PRESCALE |
(11:8) SWCLK_PRESCALE |
0x0 |
Prescale value for the input clock from pad SWCLK (1 to 16 in steps of 1) |
|
|
(2:0) SYSCLK_SRC_SEL |
(2:0) SYSCLK_SRC_SEL |
0x0 |
Controls the source of the system clock : SWCLK, RFCLK, RCCLK, or STANDBYCLK |
0x40000104 |
CLK_DIV_CFG0 |
(20:16) UARTCLK_PRESCALE |
(20:16) UARTCLK_PRESCALE |
0x0 |
Prescale value for the UART peripheral clock (1 to 32 in steps of 1) |
|
|
(10:8) BBCLK_PRESCALE |
(10:8) BBCLK_PRESCALE |
0x0 |
Prescale value for the Baseband peripheral clock (1 to 8 in steps of 1) |
|
|
(5:0) SLOWCLK_PRESCALE |
(5:0) SLOWCLK_PRESCALE |
0x2 |
Prescale value for the SLOWCLK clock (1 to 64 in steps of 1) |
0x40000108 |
CLK_DIV_CFG1 |
(27) SENSOR_CLK_DISABLE |
(27) SENSOR_CLK_DISABLE |
0x1 |
Sensor clock disable |
|
|
(26:16) SENSOR_CLK_PRESCALE |
(26:16) SENSOR_CLK_PRESCALE |
0x0 |
Prescale value for the sensor clock |
|
|
(15) CPCLK_DISABLE |
(15) CPCLK_DISABLE |
0x0 |
Charge pump clock disable |
|
|
(13:8) CPCLK_PRESCALE |
(13:8) CPCLK_PRESCALE |
0x7 |
Prescale value for the charge pump clock from the SLOWCLK clock (1 to 64 in steps of 1) |
|
|
(7) DCCLK_DISABLE |
(7) DCCLK_DISABLE |
0x0 |
DC-DC converter clock disable |
|
|
(5:0) DCCLK_PRESCALE |
(5:0) DCCLK_PRESCALE |
0x0 |
Prescale value for the DC-DC converter clock (1 to 64 in steps of 1) |
0x4000010C |
CLK_DIV_CFG2 |
(20) PWM_CLK_SRC |
(20) PWM_CLK_SRC |
0x0 |
PWM clock source |
|
|
(16) USRCLK_SRC_SEL |
(16) USRCLK_SRC_SEL |
0x0 |
USR clock source selection |
|
|
(11:0) USRCLK_PRESCALE |
(11:0) USRCLK_PRESCALE |
0x0 |
Prescale value for the USR clock (1 to 4096 in steps of 1) |