RF_REG03
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
31:30 |
RW |
MAC_CONF_MAC_TIMER_GR |
MAC timer granularity |
29 |
RW |
MAC_CONF_RX_MAC_ACT |
Switch FSM to Rx or Tx mode after an Rx mode |
28 |
RW |
MAC_CONF_RX_MAC_TX_NRX |
Switch FSM to Tx mode after an Rx mode (Rx otherwise) |
27 |
RW |
MAC_CONF_RX_MAC_START_NSTOP |
MAC timer activation after sync word detection |
26 |
RW |
MAC_CONF_TX_MAC_ACT |
Switch FSM to Rx or Tx mode after a Tx mode |
25 |
RW |
MAC_CONF_TX_MAC_TX_NRX |
Switch FSM to Tx mode after a Tx mode (Rx otherwise) |
24 |
RW |
MAC_CONF_TX_MAC_START_NSTOP |
MAC timer activation after packet transmission |
23 |
RW |
IRQ_CONF_IRQ_HIGH_Z |
Pads are set to high-Z when the IRQ is not active |
22 |
RW |
IRQ_CONF_IRQ_ACTIVE_LOW |
IRQ are active low |
21:16 |
RW |
IRQ_CONF_IRQS_MASK |
Mask to determine which IRQs are enabled (active high) |
15:13 |
RW |
FIFO_2_FIFO_THR_TX |
Threshold indicating the "almost empty" Tx FIFO state |
12 |
RW |
FIFO_2_WAIT_TXFIFO_WR |
FSM will wait a Tx FIFO write before starting the Tx mode in case of an empty Tx FIFO |
11 |
RW |
FIFO_2_STOP_ON_RXFF_OVFLW |
Stop the reception in case of a FIFO overflow |
10 |
RW |
FIFO_2_STOP_ON_TXFF_UNFLW |
Stop the transmission in case of a FIFO underflow |
9 |
RW |
FIFO_2_RXFF_FLUSH_ON_START |
Flush the Rx FIFO when the Rx mode is enabled in order to receive a packet with an empty FIFO |
8 |
RW |
FIFO_2_TXFF_FLUSH_ON_STOP |
Flush the Tx FIFO after the end of a packet transmission in order to have an empty FIFO |
7 |
RW |
FIFO_FIFO_FLUSH_ON_OVFLW |
Overflow FIFO flush control |
6 |
RW |
FIFO_FIFO_FLUSH_ON_ADDR_ERR |
Address error FIFO flush control |
5 |
RW |
FIFO_FIFO_FLUSH_ON_PL_ERR |
Packet length error FIFO flush control |
4 |
RW |
FIFO_FIFO_FLUSH_ON_CRC_ERR |
CRC error FIFO flush control |
3 |
RW |
FIFO_RX_FIFO_ACK |
Rx FIFO acknowledgement |
2:0 |
RW |
FIFO_FIFO_THR |
Threshold indicating the "almost full" Rx FIFO state |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
31:30 |
MAC_CONF_MAC_TIMER_GR |
MAC_CONF_MAC_TIMER_GR_DEFAULT |
The granularity is given by (2^(2mac_timer_gr)) x 1us |
0x2* |
29 |
MAC_CONF_RX_MAC_ACT |
MAC_CONF_RX_MAC_ACT_DISABLE |
FSM will not switch to Rx or Tx after an Rx mode |
0x0* |
|
|
MAC_CONF_RX_MAC_ACT_ENABLE |
FSM will switch to Rx or Tx after an Rx mode |
0x1 |
28 |
MAC_CONF_RX_MAC_TX_NRX |
MAC_CONF_RX_MAC_TX_NRX_DISABLE |
FSM will not switch to Tx after an Rx mode, Rx otherwise. |
0x0* |
|
|
MAC_CONF_RX_MAC_TX_NRX_ENABLE |
FSM will switch to Tx after an Rx mode, Rx otherwise. |
0x1 |
27 |
MAC_CONF_RX_MAC_START_NSTOP |
MAC_CONF_RX_MAC_START_NSTOP_DISABLE |
MAC timer is not activated at the reception of the sync word, at the end of the packet otherwise |
0x0* |
|
|
MAC_CONF_RX_MAC_START_NSTOP_ENABLE |
MAC timer is activated at the reception of the sync word, at the end of the packet otherwise |
0x1 |
26 |
MAC_CONF_TX_MAC_ACT |
MAC_CONF_TX_MAC_ACT_DISABLE |
FSM will not switch to Rx or Tx after a Tx mode. |
0x0* |
|
|
MAC_CONF_TX_MAC_ACT_ENABLE |
FSM will switch to Rx or Tx after a Tx mode. |
0x1 |
25 |
MAC_CONF_TX_MAC_TX_NRX |
MAC_CONF_TX_MAC_TX_NRX_DISABLE |
FSM will not switch to Tx after an Tx mode, Rx otherwise |
0x0* |
|
|
MAC_CONF_TX_MAC_TX_NRX_ENABLE |
FSM will switch to Tx after an Tx mode, Rx otherwise |
0x1 |
24 |
MAC_CONF_TX_MAC_START_NSTOP |
MAC_CONF_TX_MAC_START_NSTOP_DISABLE |
MAC timer is not activated at beginning of the packet, otherwise at the end of the packet transmission |
0x0* |
|
|
MAC_CONF_TX_MAC_START_NSTOP_ENABLE |
MAC timer is activated at beginning of the packet, otherwise at the end of the packet transmission |
0x1 |
23 |
IRQ_CONF_IRQ_HIGH_Z |
IRQ_CONF_IRQ_HIGH_Z_DISABLE |
The pads are not set to High-Z when the IRQ is not active |
0x0* |
|
|
IRQ_CONF_IRQ_HIGH_Z_ENABLE |
The pads are set to High-Z when the IRQ is not active |
0x1 |
22 |
IRQ_CONF_IRQ_ACTIVE_LOW |
IRQ_CONF_IRQ_ACTIVE_LOW_DISABLE |
IRQ are active high |
0x0 |
|
|
IRQ_CONF_IRQ_ACTIVE_LOW_ENABLE |
IRQ are active low |
0x1* |
21:16 |
IRQ_CONF_IRQS_MASK |
IRQ_CONF_IRQS_MASK_DEFAULT |
No IRQ enable |
0x0* |
|
|
IRQ_CONF_IRQS_MASK_TX |
Tx IRQ enable |
0x1 |
|
|
IRQ_CONF_IRQS_MASK_RX_STOP |
Rx stop IRQ enable |
0x2 |
|
|
IRQ_CONF_IRQS_MASK_RECEIVED |
Rx received IRQ enable |
0x4 |
|
|
IRQ_CONF_IRQS_MASK_SYNC |
Sync IRQ enable |
0x8 |
|
|
IRQ_CONF_IRQS_MASK_TX_FIFO |
Tx FIFO IRQ enable |
0x10 |
|
|
IRQ_CONF_IRQS_MASK_RX_FIFO |
Rx FIFO IRQ enable |
0x20 |
15:13 |
FIFO_2_FIFO_THR_TX |
FIFO_2_FIFO_THR_TX_16 |
Tx FIFO threshold is 16 samples |
0x0* |
|
|
FIFO_2_FIFO_THR_TX_48 |
Tx FIFO threshold is 48 samples |
0x1 |
|
|
FIFO_2_FIFO_THR_TX_80 |
Tx FIFO threshold is 80 samples |
0x2 |
|
|
FIFO_2_FIFO_THR_TX_112 |
Tx FIFO threshold is 112 samples |
0x3 |
|
|
FIFO_2_FIFO_THR_TX_144 |
Tx FIFO threshold is 144 samples |
0x4 |
|
|
FIFO_2_FIFO_THR_TX_176 |
Tx FIFO threshold is 176 samples |
0x5 |
|
|
FIFO_2_FIFO_THR_TX_208 |
Tx FIFO threshold is 208 samples |
0x6 |
|
|
FIFO_2_FIFO_THR_TX_240 |
Tx FIFO threshold is 240 samples |
0x7 |
12 |
FIFO_2_WAIT_TXFIFO_WR |
FIFO_2_WAIT_TXFIFO_WR_DISABLE |
FSM will not wait a Tx FIFO write before starting the Tx in case of an empty Tx FIFO |
0x0* |
|
|
FIFO_2_WAIT_TXFIFO_WR_ENABLE |
FSM will wait a Tx FIFO write before starting the Tx in case of an empty Tx FIFO |
0x1 |
11 |
FIFO_2_STOP_ON_RXFF_OVFLW |
FIFO_2_STOP_ON_RXFF_OVFLW_DISABLE |
Keep the reception in case of a FIFO overflow |
0x0* |
|
|
FIFO_2_STOP_ON_RXFF_OVFLW_ENABLE |
Stop the reception in case of a FIFO overflow |
0x1 |
10 |
FIFO_2_STOP_ON_TXFF_UNFLW |
FIFO_2_STOP_ON_TXFF_UNFLW_DISABLE |
Keep the transmission in case of a FIFO underflow |
0x0* |
|
|
FIFO_2_STOP_ON_TXFF_UNFLW_ENABLE |
Stop the transmission in case of a FIFO underflow |
0x1 |
9 |
FIFO_2_RXFF_FLUSH_ON_START |
FIFO_2_RXFF_FLUSH_ON_START_DISABLE |
Keep the Rx FIFO when the Rx is enabled |
0x0 |
|
|
FIFO_2_RXFF_FLUSH_ON_START_ENABLE |
Flush the Rx FIFO when the Rx is enabled, in order to receive a packet with an empty FIFO |
0x1* |
8 |
FIFO_2_TXFF_FLUSH_ON_STOP |
FIFO_2_TXFF_FLUSH_ON_STOP_DISABLE |
Keep the Tx FIFO after the end of a packet transmission in order to have an empty FIFO |
0x0 |
|
|
FIFO_2_TXFF_FLUSH_ON_STOP_ENABLE |
Flush the Tx FIFO after the end of a packet transmission in order to have an empty FIFO |
0x1* |
7 |
FIFO_FIFO_FLUSH_ON_OVFLW |
FIFO_FIFO_FLUSH_ON_OVFLW_DISABLE |
Keep the Rx and the FIFO in case of overflow |
0x0* |
|
|
FIFO_FIFO_FLUSH_ON_OVFLW_ENABLE |
Stop the Rx and flush the FIFO in case of overflow |
0x1 |
6 |
FIFO_FIFO_FLUSH_ON_ADDR_ERR |
FIFO_FIFO_FLUSH_ON_ADDR_ERR_DISABLE |
Keep the Rx and the FIFO in case of address error |
0x0* |
|
|
FIFO_FIFO_FLUSH_ON_ADDR_ERR_ENABLE |
Stop the Rx and flush the FIFO in case of address error |
0x1 |
5 |
FIFO_FIFO_FLUSH_ON_PL_ERR |
FIFO_FIFO_FLUSH_ON_PL_ERR_DISABLE |
Keep the Rx and the FIFO in case of packet length error |
0x0* |
|
|
FIFO_FIFO_FLUSH_ON_PL_ERR_ENABLE |
Stop the Rx and flush the FIFO in case of packet length error |
0x1 |
4 |
FIFO_FIFO_FLUSH_ON_CRC_ERR |
FIFO_FIFO_FLUSH_ON_CRC_ERR_DISABLE |
Keep the Rx and the FIFO in case of CRC error |
0x0 |
|
|
FIFO_FIFO_FLUSH_ON_CRC_ERR_ENABLE |
Stop the Rx and flush the FIFO in case of CRC error |
0x1* |
3 |
FIFO_RX_FIFO_ACK |
FIFO_RX_FIFO_ACK_DISABLE |
Rx FIFO doesn't need an acknowledgement (packet received correctly) to change its state |
0x0* |
|
|
FIFO_RX_FIFO_ACK_ENABLE |
Rx FIFO needs an acknowledgement (packet received correctly) to change its state |
0x1 |
2:0 |
FIFO_FIFO_THR |
FIFO_FIFO_THR_240 |
Rx FIFO threshold is 240 samples |
0x0* |
|
|
FIFO_FIFO_THR_208 |
Rx FIFO threshold is 208 samples |
0x1 |
|
|
FIFO_FIFO_THR_176 |
Rx FIFO threshold is 176 samples |
0x2 |
|
|
FIFO_FIFO_THR_144 |
Rx FIFO threshold is 144 samples |
0x3 |
|
|
FIFO_FIFO_THR_112 |
Rx FIFO threshold is 112 samples |
0x4 |
|
|
FIFO_FIFO_THR_80 |
Rx FIFO threshold is 80 samples |
0x5 |
|
|
FIFO_FIFO_THR_48 |
Rx FIFO threshold is 48 samples |
0x6 |
|
|
FIFO_FIFO_THR_16 |
Rx FIFO threshold is 16 samples |
0x7 |